Elevator Controller
Medium · Sequential · SystemVerilog
Design a Verilog module for a simple elevator controller FSM with states IDLE, MOVING_UP, and MOVING_DOWN. The elevator transitions between states based on {up_request} and {down_request}.
On each rising edge of {clk}, update the state. When {reset} is asserted, the FSM immediately returns to IDLE. The output {state} is an encoding where $00$ = IDLE, $01$ = MOVING_UP, and $10$ = MOVING_DOWN.