Dot Product
Easy · Sequential · SystemVerilog
Implement a module that produces the dot product (scalar product) of two length-$3$ vectors, A = [a1, a2, a3] and B = [b1, b2, b3]. The module has one port {din} for entering the input sequence and two outputs, {run} and {dout}, which return the computation status and dot product.
Assume inputs arrive in the following order: a1, a2, a3, b1, b2, b3. Once the $6$th number has been registered, {run} is asserted and {dout} returns the value $a1*b1 + a2*b2 + a3*b3$. In subsequent cycles, {run} is de-asserted while {dout} holds its previous valid value until the next six inputs are captured.
On any rising edge of {clk}, if {resetn} is low, internal registers are cleared. When {resetn} returns high, {run} is asserted and {dout} is $0$.