Divisble by 5
Medium · Sequential · SystemVerilog
Design a module that determines whether an input value is evenly divisible by five.
The input value is of unknown length and is left-shifted one bit at a time into the module via {din}. The module should output $1$ on {dout} if the current cumulative value is evenly divisible by five, and $0$ otherwise.
When {resetn} is asserted, all previous bits seen on the input are no longer considered. The $0$ seen during reset should not be included when calculating the next value. During reset, {dout} must be $0$.
This problem is tricky, so it may help to think in terms of modulus and remainder states.