Divide by Evens Clock Generator
Easy · Sequential · SystemVerilog
Design a module that, given an input clock signal, generates three output clock signals with $2x$, $4x$, and $6x$ the period of the input clock.
When {resetn} is active, the module should reset all clocks to $0$. When {resetn} becomes inactive again, the module should start a new period for each output clock. Specifically, if {resetn} became active in the middle of an output clock's period, the next period should restart instead of continuing from where the interrupted period left off.