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Direct-Mapped Write-Back Cache

Hard · Sequential · SystemVerilog

Design a direct-mapped write-back cache with a synchronous memory handshake interface.

## Address Decomposition

{cpu_addr} is partitioned into two fields: the upper $\text{ADDR\_WIDTH} - \text{INDEX\_BITS}$ bits form the tag, and the lower INDEX_BITS bits form the index. The index selects one of $2^\text{INDEX\_BITS}$ cache lines. Each cache line stores a DATA_WIDTH-bit data word, a tag of $\text{ADDR\_WIDTH} - \text{INDEX\_BITS}$ bits, a valid bit, and a dirty bit.

## Hit Detection

The selected cache line is a **hit** when its valid bit is set and its stored tag equals the tag field of {cpu_addr}. On a hit, the cache responds in the same cycle with {cpu_stall} $= 0$:

- **Read hit** ({cpu_re} $= 1$): {cpu_rdata} is driven combinationally with the stored word. - **Write hit** ({cpu_we} $= 1$): the stored word is updated to {cpu_wdata} and the dirty bit is set; {cpu_rdata} is unspecified.

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