CRC-16/CCITT Generator
Hard · Sequential · SystemVerilog
Design a byte-serial CRC-16/CCITT generator that processes one byte per clock cycle, accumulates a running CRC over a frame of arbitrary length, and asserts {crc_valid} with the final checksum one cycle after the last byte is presented. The module supports back-to-back frames with no idle cycles required between them.
## CRC Parameters
The generator uses the CCITT variant of CRC-16:
- Polynomial: $x^{16} + x^{12} + x^{5} + 1$ (hex representation 0x1021) - Initial seed: 0xFFFF - Byte bit order: MSB-first (bit 7 of {data_in} is processed before bit 0) - No final XOR, no reflection
The standard iterative update rule for one bit is: if the current top bit of the CRC register is 1, shift left by one, feed in the incoming bit, then XOR with 0x1021; otherwise, shift left by one and feed in the incoming bit with no XOR. Applied 8 times per byte (MSB-first), this yields the updated 16-bit CRC register after each byte.
## Input Handshake