Counter
Easy · Sequential · SystemVerilog
Build a module which controls a counter.
The counter starts counting when the start button (start) is pressed (pulses) and increases by 1 every clock cycle. When the stop button (stop) is pressed, the counter stops counting. When the {reset} button is pressed, the {count} resets to 0 and the counter stops counting.
If {count} ever reaches MAX, then it restarts from 0 on the next cycle.
{stop}'s functionality takes priority over {start}'s functionality, and {reset}'s functionality takes priority over both {stop} and {start}'s functionality.