Conditional Adder
Easy · Combinational · SystemVerilog
Design a module for Conditional Addition. The module performs conditional addition based on the value of {s}. The output {Z} is determined by adding pairs of input signals. If {s} is $1$, {Z} is the sum of {A} and {B}. If {s} is $0$, {Z} is the sum of {C} and {D}.