Carry-Save Adder (3:2 Compressor)
Hard · Combinational · SystemVerilog
Implement a parameterized combinational **carry-save adder (CSA) 3:2 compressor** that reduces three N-bit unsigned operands to two N-bit carry-save outputs plus the final N+2-bit arithmetic sum.
A carry-save adder is a foundational digital arithmetic building block. Instead of propagating carries across bit positions, a CSA evaluates each bit column independently using a single full-adder cell, producing a "sum bit" and a "carry bit" per column. This eliminates the critical carry-chain path and is the core reduction step in multiplier arrays and Wallace tree multi-operand adders.
**Module interface**
The module is purely combinational — no clock, no reset.
```systemverilog module wallace_tree_adder #( parameter N = 8 // bit width of each operand (2–16) ) ( input logic [N-1:0] a, input logic [N-1:0] b, input logic [N-1:0] c, output logic [N-1:0] sum_bits, output logic [N-1:0] carry_bits, output logic [N+1:0] sum ); ```
**Output definitions**