Bubble Sort
Hard · Sequential · SystemVerilog
Design a module that implements the bubble sort algorithm within one cycle. The module takes {din}, an unsigned word; {sortit}, a signal asserted to start a new sort operation; and {resetn}, a synchronous active-low reset. The output {dout} is a concatenated vector of $8$ unsigned words captured in the module's memory when {sortit} is asserted.
Input {sortit} is asynchronous from another module, so assume there is no need to flop it. Inputs are registered only when {sortit} = $0$ and ignored otherwise. {dout} is valid only when {sortit} = $1$; otherwise {dout} must be $0$. The output vector is sorted in descending order: the most significant chunk corresponds to the smallest value, while the least significant chunk corresponds to the largest value.
During reset, {dout} must be $0$.