Blog

• How I Got an ASIC Engineering Internship at Amazon

  July 18, 2026 · 5 min read

  It took me over a year and a half to break into hardware with just a bachelor's degree. What the interviews actually looked like, where I choked, and what actually mattered.

• Setup and Hold Time Explained: Violations and Fixes

  July 11, 2026 · 9 min read

  Setup and hold time explained: the timing equations, how to fix setup and hold violations, even on the same path, and why a slower clock never fixes hold.

• Blocking vs Non-Blocking Assignments in Verilog: = vs <=

  July 10, 2026 · 8 min read

  Blocking vs non-blocking assignments in Verilog: when to use = vs <=, why <= prevents race conditions, the two bugs = causes, and the Cummings guidelines.

• Async FIFO in SystemVerilog: Why Binary Pointers Break and How Gray Code Fixes Them

  June 29, 2026 · 12 min read

  Build a dual-clock async FIFO in SystemVerilog the right way: gray-coded pointers, 2-FF synchronizers, and the extra-bit trick that makes full/empty detection provably safe.

• CRC-32 in Hardware: Why the Serial LFSR Fails at Line Rate and How the Parallel XOR Tree Fixes It

  June 27, 2026 · 8 min read

  A serial CRC-32 LFSR tops out at 125 Mb/s at 125 MHz — far below Gigabit Ethernet. Learn how to derive the 8-bit parallel XOR tree from the same recurrence, with real synthesis area and frequency numbers.

• Why Your PWM Glitches and How a Shadow Register Fixes It

  June 26, 2026 · 12 min read

  Naive PWM produces a runt or stretched pulse when you update the duty cycle mid-period. Learn why — and how a shadow register that latches only at period-end fixes it with just 8 extra flip-flops.

• AXI4-Lite Slave in SystemVerilog: AWVALID and WVALID Order

  June 25, 2026 · 7 min read

  AXI4-Lite write handshake: why the master must not wait for AWREADY before WVALID, the template bug that drops writes, and a correct SystemVerilog slave.

• I2C Master in SystemVerilog: Why Your Flat FSM Breaks on Real Hardware (and the Two-Level Fix)

  June 23, 2026 · 9 min read

  Flat FSM vs. two-tier sequencer I2C master in SystemVerilog: sky130 synthesis shows 2592 vs 3108 µm², and only one design survives clock stretching on real hardware.

• SPI in Four Modes: The One Edge Rule That Every Tutorial Gets Wrong

  June 19, 2026 · 11 min read

  Synthesized on sky130, the generalized four-mode SPI master lands at 336 cells, 1134.8 μm², and a maximum frequency of 481 MHz. The mode-locked variant — Mode 0 only, CPOL and CPHA hardwired to zer…

• UART Transmitter and Receiver in SystemVerilog: Mid-Bit Sampling, Metastability, and 8N1 by the Numbers

  June 18, 2026 · 12 min read

  Build a synthesizable 8N1 UART in SystemVerilog: understand why naive oversample-counter resets put your samples off-center, how a 2-FF synchronizer prevents metastability on the RX pin, and what the design costs in LUTs and flip-flops.

• Round-Robin Arbiter in SystemVerilog: Starvation, the Rotating-Mask Fix, and Real Synthesis Numbers

  June 17, 2026 · 10 min read

  Build a starvation-free round-robin arbiter in SystemVerilog using the rotating-mask technique, with synthesis numbers comparing area and Fmax against a fixed-priority baseline at N=4 and N=8.

• Pipelining a 32-bit Multiplier in SystemVerilog: Latency, Throughput, and the Area-Speed Tradeoff

  June 16, 2026 · 7 min read

  How to pipeline a 32x32 unsigned multiplier in SystemVerilog: see real synthesis numbers (LUTs, FFs, Fmax) for combinational vs 4-stage designs and learn exactly when the latency cost is worth paying.

• Clock Domain Crossing in SystemVerilog: 2-FF Synchronizer, Async FIFO, and the Multi-Bit Trap

  June 15, 2026 · 11 min read

  Learn when a 2-FF synchronizer is safe, why applying it to a bus silently corrupts data, and how an async FIFO with Gray-code pointers fixes it -- with synthesized area numbers.

• What Synthesis Actually Does to Your FSM State Encoding (and How to Override It)

  June 14, 2026 · 15 min read

  Synthesis tools silently re-encode your FSM state register. Learn when Vivado auto-selects one-hot vs. binary, which attribute forces your choice, and where Gray code actually wins.

• Carry-lookahead isn't the fast adder you were sold

  June 13, 2026 · 10 min read

  Carry-lookahead is taught as the fast adder, but fan-in blows up with width. Synthesized 16-bit numbers show what you actually buy in area and timing.

• Synchronous FIFO Design in SystemVerilog: From Naive Counter to Extra-Bit Pointer

  June 13, 2026 · 9 min read

  Master synchronous FIFO design in SystemVerilog: learn the extra-bit pointer trick that eliminates full/empty subtraction logic, enables BRAM inference, and adds almost-full/almost-empty threshold flags.