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title: "Setup and Hold Time: The Constraint Every Engineer Knows and the Asymmetry Most Miss" date: 2026-07-11 slug: setup-hold-time-digital-design tags: [digital-design, timing, fpga, vlsi]
Slack (VIOLATED) : -0.045ns (arrival time - required time)
I've watched engineers fix this — insert a buffer, rerun timing, close the report — without stopping to ask why a hold violation is categorically different from the setup violation they fixed earlier in the same session. The two constraints look like a matching pair on every timing diagram ever drawn, but they have different physics, different failure modes, and critically, only one of them can be patched after silicon comes back from the fab.
A setup violation is a performance problem. A hold violation is a correctness problem, and that distinction matters more than most timing explanations let on.
Everyone has the two-sentence definition memorized: data must be stable some time before the clock edge (setup), and some time after it (hold). That's accurate as far as it goes. What it doesn't explain is why the two behave differently under pressure, or what your options are when you find one at tape-out.
A flip-flop has a window around every clock edge where the D input must not change. The setup time Tsu is the minimum duration before the clock edge during which D must be stable. The hold time Th is the minimum duration after the clock edge during which D must remain stable. Together they form the aperture time Ta = Tsu + Th — the total forbidden window around the edge.
The 74HC74, a standard CMOS D flip-flop, specifies Tsu = 16 ns at 4.5 V supply and Th = 3 ns constant across all supply voltages from 2 V to 6 V. Setup time shrinks as voltage rises — more overdrive, faster transistors — but hold time doesn't move with it, and that voltage independence is the first indication these constraints have different physics driving them. The older 74LS74 TTL family had Tsu = 20 ns and Th = 0 ns — a different internal topology with effectively no hold requirement. A Xilinx Kintex UltraScale+ CLB flip-flop (FDRE) has a setup time of approximately 180 ps — roughly 100× faster than the 74HC74, accumulated over about 30 years of CMOS scaling.
Those numbers reflect real physics. A D flip-flop is a master-slave latch pair. The master is transparent when the clock is low — data passes through freely. When the clock goes high, the master closes and the slave opens to propagate the captured value to Q.
Setup time is the window the master latch needs to fully commit to the incoming data before the clock edge closes it. The internal cross-coupled inverters have to settle to a valid state: whichever side is biased higher must drive the other past its switching threshold before the master gets isolated from the input. One or two gate delays of internal propagation is all it takes — but if new data arrives too close to the edge, the inverters are still resolving when the master closes, and they end up balanced at an unstable midpoint voltage between VIL and VIH. That's metastability, and I'll get to what it means in the transistors in a moment.
The timing check captures this directly: Tclk ≥ Tpcq + Tpd + Tsu, where Tpcq is the clock-to-Q propagation delay of the launch flip-flop, Tpd is the worst-case (maximum) combinational delay between flip-flops, and Tsu is the setup requirement of the capture flip-flop. Rearranged for maximum frequency, including clock skew Tskew — positive skew meaning the capture flip-flop's clock arrives later than the launch flip-flop's, giving data more time to traverse the path and reducing the effective requirement:
fmax = 1 / (Tpcq + Tpd + Tsu - Tskew)
The clock period is what you're solving for, which is exactly why setup violations are frequency-dependent. Increase Tclk and the constraint eventually closes.
Hold time is a different constraint with different physics. The master just closed — but its isolation isn't instantaneous. For a brief window after the clock edge, called the clock-to-Q contamination delay Tccq, the master is still reachable from the D input. Data arriving through a short combinational path during those first Tccq picoseconds can corrupt the value the master just captured.
This is the insight almost every introductory explanation skips: hold violations are caused by fast paths, not slow ones. The relevant delay is the contamination delay Tcd — the fastest possible traversal of the combinational logic at best-case process and temperature conditions. The hold check is:
Tccq + Tcd ≥ Th
There is no Tclk in that equation. The clock period is completely absent — the hold check is a same-cycle event. The contamination delay path arrives at the capture flip-flop before the preceding clock edge has finished isolating the master. Running the clock slower gives the data path more time to settle before the next edge, which does nothing about how fast it moved relative to the current one.
A direct connection between two flip-flops with no combinational logic is the canonical hold hazard: Tcd = 0, so the check collapses to Tccq ≥ Th. If the flip-flop's hold requirement exceeds its own contamination delay — which is common — any back-to-back register chain violates hold regardless of clock rate: 1 MHz, 1 Hz, DC. The clock speed doesn't enter the picture.
"The output is undefined" is accurate and useless — the flip-flop's cross-coupled inverters form a bistable circuit with two stable states and one unstable equilibrium. When data arrives during the aperture window, those inverters get caught at the unstable point, balanced at a voltage between VIL and VIH where neither side wins. Resolution is probabilistic and exponential: the probability of still being metastable after time t follows P ≈ exp(-t/τ), where τ is the technology's metastability time constant — approximately 20–50 ps for modern CMOS.
The danger isn't just receiving a random 0 or 1. A sustained intermediate voltage propagates downstream and drives subsequent logic into unpredictable states — failures that show up as intermittent hardware bugs, non-reproducible, temperature-sensitive, timing-load-sensitive, the hardest category to chase. Synchronizer designs exploit the exponential decay by giving the metastable flip-flop an entire clock period before its output gets sampled. At 500 MHz that's 2 ns of resolution time, and exp(-2000 ps / 30 ps) ≈ 10⁻²⁹. By the time the downstream logic sees the output, it's resolved with overwhelming probability.
Vivado makes this concrete in its timing reports. The timing summary gives four numbers: WNS (Worst Negative Slack, setup), TNS (Total Negative Slack), WHS (Worst Hold Slack), and THS (Total Hold Slack). Negative WNS means setup violations; negative WHS means hold violations. Both have to be zero or positive before you tape out.
For setup: slack = Tclk - Tpcq - Tpd - Tsu. Negative slack means the path is too slow for the target period.
For hold: slack = Tccq + Tcd - Th. Negative slack means data arrived too early.
Setup analysis runs at maximum delay at the slow process corner — worst-case slow delays, pessimistic process and temperature conditions — because setup violations come from paths that are too slow. Hold analysis also runs at the slow process corner, but at minimum delay within that corner: same process conditions, but now Vivado is asking what is the fastest this path could possibly be, because hold violations come from data that arrives too fast. Both analyses use the slow process corner. The hold report line says "Min at Slow Process Corner" — minimum delay within that corner — not a different fast corner. The worst hold hazard is the fastest path through your design under slow-corner device parameters, and that is exactly what Vivado checks.
A real setup violation in Vivado looks like this:
Slack (VIOLATED) : -0.239ns (required time - arrival time)
Path Type: Setup (Max at Slow Process Corner)
Data Path Delay: 4.180ns
And a hold violation:
Slack (VIOLATED) : -0.045ns (arrival time - required time)
Path Type: Hold (Min at Slow Process Corner)
Data Path Delay: 3.443ns
The sign convention differs because they measure different things. Setup slack is how much headroom remains before you've consumed the full clock period. Hold slack is how much margin exists between when data arrives and the earliest it could have safely arrived relative to the clock edge.
The fixes map directly onto those slack definitions. Setup violations mean the data path is too slow — reduce Tpd. Use higher drive-strength cells, reduce logic depth, or pipeline the path to split a long combinational chain across multiple cycles; slowing the clock works too if you have margin to give. Hold violations mean the opposite: the data path is too fast, so increase Tcd by inserting delay buffers, using lower drive-strength cells, or routing through more interconnect. Never remove logic from a hold-violating path — it reduces Tcd and makes things worse.
Clock skew cuts in opposite directions for the two checks, which you can read directly from the fmax formula. Positive skew — where the capture flip-flop's clock arrives later than the launch flip-flop's — subtracts from the setup denominator, giving data more time to traverse the combinational path. That same later capture edge shrinks the guard time for hold. Every knob you turn to fix one constraint exerts counter-pressure on the other.
The genuinely difficult case: a path that simultaneously violates both setup and hold. This happens when a path has a large spread between its maximum delay and its minimum delay at the slow corner. Inserting buffers to fix hold pushes the slow path further over the setup limit. Removing buffers to fix setup makes hold worse. The only clean resolution is to restructure the path itself — either through architectural changes or by moving the flip-flops closer together in the netlist — so that spread narrows.
All of this assumes you're pre-silicon. When an ASIC comes back from the fab with timing violations in characterization, which one you have determines everything. A setup violation: lower the rated operating frequency until the slow paths meet timing. The chip ships at 400 MHz instead of 500 MHz. You've paid in performance, but the design is functionally correct at the lower frequency.
A hold violation is a different situation. Lowering frequency does nothing — the data is moving too fast relative to the clock edge, and a slower clock gives it no less time to do so. The only salvage options are a metal-layer ECO — adding resistance through routing changes if the metal stack permits — or a complete re-spin. This is what VLSI engineers mean when they say a hold violation "dumps the chip."
That's why the interview question at Intel, Qualcomm, and similar companies — "which is harder to fix, a setup violation or a hold violation, and why?" — has a context-dependent answer. Pre-silicon, hold violations are typically easier to close: you insert buffers, adding delay without affecting frequency. Post-silicon, the situation inverts. A setup violation costs you a speed bin. A hold violation costs you the chip.
If you want to practice writing RTL that actually closes timing on both setup and hold, Logicode has a library of timed synthesis problems.